The present invention relates to an asynchronous transfer mode switching system adapted advantageously to high-speed transmission of data including large quantities of computer data and image data.
A steady expansion of today's information-oriented society has entailed significant increases in the volume of high-speed data including computer signals and digitized video signals in addition to conventional low-speed data such as telephone and fax signals. To cope with the need to transmit all these data efficiently in any way desired, intensive efforts have been made to develop communication systems of broader band characteristics and ever-higher levels of efficiency. Already, in the field of local networks, broadband communication systems are in place and operating at a growing number of installations. In the field of public telecommunication, varieties of networks (e.g., telephone, facsimile and data communication networks) each separately developed are beginning to be integrated into what is known as a B-ISDN (Broadband Integrated Services Digital Network). The B-ISDN unites the existing networks in a broadband framework by means of standardized interfaces.
One technique now drawing attention as an effective way for implementing broadband communication systems and the B-ISDN is a digital communication technique that functions in asynchronous transfer mode (abbreviated to "ATM" hereunder). The ATM communication technique utilizes fixed-length packets called cells whose length is set to 53 bytes each by international standards. Of the 53 bytes making up a cell, 48 bytes are used for transmitting data proper and the remaining five as a header for accommodating address information.
Whereas conventional time-division communication setups fix the number of cells and the time slots assigned to these cells for each communication channel within a frame of a constant cycle, the ATM communication technique allows the cell count and the time slot assignments to vary depending on the quantity of data to be transmitted and on the data transfer rate in effect. More specifically, the ATM communication technique effects data transmission by having the cells accommodated in the time slots determined by the standard clock cycle of the network in question. Because each cell is accommodated whenever an empty time slot is found, the time slots are necessarily varied. That is, the cells are transferred asynchronously (i.e., in asynchronous transfer mode). Cells for communication channels are arranged into a string according to the number of cells and the sequence in which the cells are generated. The ATM communication technique deals adequately with any abrupt demand for the transfer of huge quantities of data, and performs data transfers in accordance with specific data rates required.
FIG. 7 shows a typical switching system disclosed in the Proceedings of the IEEE, Vol. 78, No. 1 (January 1990), pp. 133-167. In FIG. 7, a switch 1 comprises a space-division switch array 2 (whose input side alone is depicted here for simplification) having stages of numerous unit switches 20-11 through 20-nm. The unit switches 20 include input terminals and output terminals (generally constituting a 2-input, 2-output terminal makeup), and are interconnected as shown according to a desired design concept. The input terminals of each of the unit switches 20-11 through 20-n1 in the first stage (input stage) are connected to the output terminals of any one of input interface circuits 40-1 through 40-n. The output terminals of each of the unit switches in the last stage (output stage, not shown) are connected to the input terminals of any one of output interface circuits 41-1 through 41-n.
The input interface circuits 40-1 through 40-n are each connected to any one of n transmission lines (not shown) on the input side. These circuits are used to remove overhead information (sync signal, error control signal, monitor signal, etc.) from a cell string which is synchronous with the system clock so as to extract the string alone that is the synchronous cell string C for output.
The synchronous cell strings C (simply called "cell strings C" hereunder)from the transmission lines are sent into the unit switches 20-11 through 20-n1 of the first stage via the input interface circuits 40-1 through 40-n. The cell strings C are subjected to a predetermined cell switching operation (i.e., selective switching of transfer channels) in accordance with the address information held in the headers of individual cells. After that, the switched cell strings C are output from the unit switches of the last stage, not shown. The switched cell string C thus output is sent to an appropriate one of the output interface circuits 41-1 through 41-n. In turn, the output interface circuits 41-1 through 41-n add overhead information to the switched cell strings C (the switched cell string C comprises cells for a communication channel set for the same destination), thereby converting the switched cell strings C into transfer-ready signals. Each of the output interface circuits 41-1 through 41-n is connected on the output side to an external transmission line (not shown) linked to a predetermined destination. The converted signals are placed onto the external transmission lines for specific destinations.
The unit switches 20-11 through 20-nm are identical in their structure. FIG. 8 depicts the structure of one unit switch 20. A switching operation is carried out by a pair of selector circuits 24 under control of an address control circuit 22. The input cell strings C are stored temporarily in a pair of input latch circuits 21. Every time a switching operation is performed, the input latch circuit 21 reads one cell. Given the cell read by the input latch circuit 21, the address control circuit 22 interprets the address information in the header of the cell to determine its destination and outputs a selector control signal S accordingly to control the selector circuits 24. After being switched by the selector circuits 24, the cells are sent to the unit switches of the next stage, not shown in FIG. 8. The input latch circuits 21 are fed with clock pulses Ck from a clock generator 60. The input latch circuits 21 store and read each cell in synchronism with the clock pulses Ck. On receiving the cells from the input latch circuits 21, the selector circuits 24 perform the switching operation in synchronism with the clock pulses Ck to output synchronous cells.
The conventional switching method illustrated in FIGS. 7 and 8 is incapable of averting differences in arrival time between individual cells as they reach specific unit switches, the differences being attributable to the differences in length between transmission lines interconnecting the unit switches arranged side by side. Similar time differences also occur due to the disparities in characteristic between the devices constituting the unit switches as well as to the parameters of temperature and other ambient conditions. Clock pulses also entail differences in arrival time between individual circuits as the pulses travel over wires of different lengths. Time differences of the above kind can trigger malfunction in a switching system that operates synchronously as a whole using the same timing based on clock pulses. For this reason, conventional switching systems are required to set clock pulse cycles to allow for a predicted maximum time difference between cells. The settings are made to match the cell arrival times with the start of switching (set by the clock pulses), so that each switching operation takes place after the cell having the maximum time difference has arrived. Conventional system design thus requires setting the maximum time difference as a timing margin which is included in the clock pulse cycle. With the time differences absorbed by the time margin thus established, possible malfunction of the system is avoided. However, to have the timing margin included in the clock pulse cycle requires prolonging the clock cycle by that margin, which reduces the switching operation speed. The drop in the switching operation speed in turn lowers the throughput of data switching (i.e., number of all bits output by the switching system per unit time). Another disadvantage resulting from the inclusion of the timing margin is the need for complicated and difficult timing design.